The present invention relates to a dynamic semiconductor memory device which can be integrated at a high density.
In the one-transistor memory cell which is formed of one MOS transistor and one capacitor, the memory cell occupies a small area. Therefore, this type of memory cell is advantageously used in the case of manufacturing semiconductor memories with a high density or high integration. For example, it is frequently used to form a dynamic random access memory (DRAM). Recently, the studies have been made to reduce the area occupied by the capacitor of the one-transistor memory cell and design the proper structure of this memory cell for high density. As such a kind of memory cell, vertical capacitor cell, folded capacitor cell, and corrugated capacitor cell have been known. For example, the vertical capacitor cell has been published in, T. Furuyama and J. Frey, "A VERTICAL CAPACITOR CELL FOR VLSI DRAM'S", Symposium on VLSI Technology, Technical Digest, 1984, page 16. The folded capacitor cell has been introduced in, Wada et al, "A Folded Capacitor Cell For Future Megabit DRAMs", IDEM, 1984. The corrugated capacitor cell has been published in International Solid State Circuit Conference (ISSCC) in 1984. This corrugated capacitor cell is constituted such that a narrow groove is formed perpendicularly to the wafer in the central portion of the capacitor region and the charges are stored in the capacitor formed of opposite side surfaces of this groove, thereby increasing an amount of signal charges which can be stored in the capacitor. On the other hand, the vertical capacitor cell is constituted such that a groove is formed in the wafer at the position corresponding to the element isolation region and an insulation region is formed in the bottom portion of this groove to isolate the opposing side walls from each other and the charges are stored in the capacitor formed using one of the opposing side walls.
The vertical capacitor cell, folded capacitor cell, and corrugated capacitor cell have capacitors of large capacitances in small occupied areas, so that they are fitted for high integration.
FIG. 1A diagrammatically shows a plane pattern of part of a conventional memory having vertical capacitors. FIG. 1B shows a cross sectional structure which is derived by cutting away part of the memory shown in FIG. 1A along the A--A line. This memory includes p-type semiconductor substrate 1; groove 2 formed in substrate 1; p.sup.+ -type element isolation region 3 formed in the bottom portion of groove 2 by ion implantation; n-type semiconductor region 4 formed in part of the surface of substrate 1 and side wall of groove 2; insulation layer 5 formed on substrate 1; and word lines 6 which are formed in insulation layer 5 and also serve as MOS transistor gate electrodes. Word lines 6 are formed of polycrystalline silicon, silicide, polycide, refractory metal such as molybdenum, or the like. In addition, polycrystalline silicon layer 7 is formed in groove 2 and constitutes a capacitor in cooperation with n-type region 4 formed in the side wall of groove 2. Bit line 8 is formed on insulation layer 5 in a direction perpendicular to word lines 6. Part of bit lines 8 are connected to the portions serving as one end (drain) of the MOS transistor in n-type semiconductor region 4 by contact areas 9. Silicide, polycide, refractory metal, aluminum, or the like is used as a material of bit line 8. Element isolation region 10 is formed by embedded silicon dioxide. In FIG. 1A, the hatched region surrounded by dot-and-dash line denotes one memory cell region.
As will be understood from FIGS. 1A and 1B, the vertical capacitor cell has conventionally been handled as a memory cell whose plane pattern and structure are fitted to constitute a memory of open bit line structure. The open bit line structure means that a pair of bit lines are arranged to extend in the opposite directions with a sense amplifier connected between them.
On the other hand, there is a memory structure called folded bit line structure. The folded bit line structure denotes that a pair of bit lines are arranged adjacently or closely in parallel with each other and connected at one end to a sense amplifier. FIG. 2A shows a plane pattern of the memory region including, for example, four memory cells which are suitable for the folded bit line structure and are frequently used in the dynamic RAM which is at present commercially available. FIG. 2B shows a cross sectional structure taken along the B--B line of FIG. 2A. This memory includes p-type semiconductor substrate 21; n-type semiconductor regions 23 formed in the surface area of substrate 21; insulation layer 24 formed on the substrate surface; word lines 25 which are formed in insulation layer 24 and also serve as MOS transistor gate electrodes; capacitor electrodes 26 formed in insulation layer 24; and bit lines 27 formed on insulation layer 24 in a direction perpendicular to word lines 25. Part of bit lines 27 are connected to the portions serving as one end of the MOS transistor in n-type semiconductor region 23 by contact areas 28. In addition, in the capacitor regions of the hatched portions in FIG. 2A, capacitor electrode 26 constitutes a capacitor in cooperation with an n-type region (not shown) formed in the surface area of substrate 21. As will be understood from FIGS. 2A and 2B, to realize the conventional folded bit line structure, two word lines 25 per memory cell must be arranged in the lateral direction in the same layer and wired. In this respect, it is considered improper to use, in the memory of the folded bit line structure, the vertical capacitor cell in which the memory cell pitch is small in the direction of bit line.
FIG. 3A shows a plane pattern of part of a DRAM having folded capacitor cells. FIG. 3B shows a cross sectional structure taken along the C--C line of FIG. 3A.
This DRAM is constituted such that word lines WL.sub.1, WL.sub.2, . . . , WL.sub.8 are arranged in a vertical direction on a semiconductor substrate 31 formed of, e.g., p-type silicon, and bit lines BL.sub.1 to BL.sub.4 are arranged in a horizontal direction over those word lines. MOS transistors formed in regions 32 surrounded by dash-and-two-dot lines or MOS capacitors formed in hatched regions 33 surrounded by dash-and-dot lines are arranged at the positions corresponding to the crossing points of word lines WL.sub.1 to WL.sub.8 and bit lines BL.sub.1 to BL.sub.4. The source region of the MOS transistor is connected to the MOS capacitor which is formed adjacent the MOS transistor in the data line direction. The drain region of the MOS transistor is connected to one of bit lines BL.sub.1 to BL.sub.4 through contact hole 34.
In addition, as clearly shown in FIG. 3B, grooves GV.sub.1 to GV.sub.3 are each formed in the memory cell isolation region between adjacent two of bit lines BL.sub.1 to BL.sub.4 formed over semiconductor substrate 31. p.sup.+ -Type impurity regions 35 are formed in the bottom surfaces of grooves GV.sub.1 to GV.sub.3. Oxide layers 36 are deposited on grooves GV.sub.1 to GV.sub.3. Due to grooves GV.sub.1 to GV.sub.3, the memory cell regions surrounded by thick solid lines in FIG. 3A become relatively convex as compared with the other regions. In capacitor region 33, n.sup.- type impurity region 37 is formed on the top and side surfaces of the convex portion of semiconductor substrate 31. Capacitor electrode 39 of polycrystalline silicon is formed through oxide layer 38 over n.sup.- type impurity region 37 formed on the top and side surfaces of the convex portion, thereby constituting the MOS capacitor.
A method of manufacturing the DRAM shown in FIGS. 3A and 3B will then be described with reference to FIGS. 4A to 4D. Grooves GV.sub.1 to GV.sub.3 are formed in semiconductor substrate 31 of p-type silicon having a resistance of about 10 .OMEGA.-cm by a reactive ion etching method as shown in FIG. 4A. B ions are implanted into the bottom surfaces of grooves GV.sub.1 to GV.sub.3 by ion implantation, thereby forming p.sup.+ -type impurity regions 35.
Next, oxide layer 36 is deposited on the whole surface to completely cover the grooves. Thereafter, oxide film 36 is etched to expose the top surfaces of the convex regions of semiconductor substrate 31 sandwiched by grooves GV.sub.1 to GV.sub.3 as shown in FIG. 4B.
Then, capacitor regions 33 are patterned by a photo etching process (PEP) and only oxide layers 36 in grooves GV.sub.1 to GV.sub.3 in capacitor regions 33 are selectively removed by a reactive ion etching method as shown in FIG. 4C. In this manner, the top and side surfaces of the convex regions of semiconductor substrate 31 in capacitor regions 33 are exposed. As ions are implanted into the top and side surfaces of the exposed convex portions due to ion implantation to form n.sup.- -type impurity regions 37. Subsequently, as shown in FIG. 4D, oxide films 38 are formed on the surface of n.sup.- -type impurity regions 37 by thermal oxidation. Further, capacitor electrodes 39 of polycrystalline silicon are formed on oxide layers 38. As described above, the MOS capacitor part of which was embedded in the groove is formed in capacitor region 33.
Further, an insulation layer 40 is formed on capacitor electrode 39. A gate oxide layer is formed on the convex region of the memory cell region excluding capacitor region 33. Word lines WL.sub.1 to WL.sub.8 of polycrystalline silicon are formed on insulation layers 40 and gate oxide layers. The source and drain regions are formed in memory cell regions 32 by ion implantation, thereby forming the MOS transistors. An insulation layer 41 between layers is further formed on the whole surface and contact holes 34 are formed at predetermined positions. Thereafter, bit lines BL.sub.1 to BL.sub.4 of aluminum are formed. Thus, the DRAM shown in FIGS. 3A and 3B are obtained.
FIG. 5 shows a perspective view of the DRAM of FIGS. 3A and 3B including a partial cross section of one memory cell. The width of groove GV formed in semiconductor substrate 31 is equal to the sum of a thickness a of capacitor electrode 39 embedded in groove GV, a length b of the extended portion formed on oxide layer 36 deposited in groove GV, and an interval c between capacitor electrode 39 and memory cell region 32 where a MOS transistor TR is formed. Now, in the case of manufacturing the DRAM using a rule of 0.8 .mu.m, EQU a=0.4 .mu.m EQU b=0.3 .mu.m EQU c=0.3 .mu.m
are respectively necessary, so that the width (a+b+c) of groove GV becomes 1.0 .mu.m. In this case, a thickness (b+c) of oxide layer 36 between capacitor electrode 39 embedded in groove GV and memory cell region 32 where MOS transistor TR is formed becomes 0.6 .mu.m.
However, the thickness of about 0.6 .mu.m of oxide layer 36 causes the phenomenon that a side surface portion B which is in contact with groove GV of memory cell region 32 is inverted due to the potential of capacitor electrode 39. In other words, a parasitic transistor is formed, in which capacitor electrode 39 in groove GV serves as a gate electrode, oxide layer 36 in groove GV serves as a gate oxide layer, and source and drain regions (SR and DR) of MOS transistor TR in the memory cell region respectively serve as source and drain regions. Due to conduction of this parasitic transistor, a leak path is formed between the source and drain of MOS transistor TR and the data in the memory cell is broken.
To prevent formation of the leak path due to the parasitic transistor, it is necessary to set the thickness (b+c) of oxide layer 36 serving as the gate oxide layer to a value of 1.2 .mu.m or more. In this case, the width (a+b+c) of groove GV becomes 1.6 .mu.m or more, resulting in an increase in thickness of at least 0.6 .mu.m. When now considering the DRAM of 4 kbits having 2048.times.2048 memory cells, the whole chip width is increased by about 1.2 mm (=0.6 .mu.m.times.2048).
As described above, the DRAM in which part of memory capacitor CAP is embedded in the groove formed in the semiconductor substrate has the problem that the chip area is increased in order to prevent occurrence of the leak path due to the parasitic transistor. Moreover, the increase in the chip area is proportional to integration degree of the DRAM, so that it becomes a critical problem with an increase in integration.
In general, the memory of the folded bit line structure is constituted such that a pair of bit lines are adjacently arranged in parallel with each other; therefore, it has the advantage that noise generated due to unbalance in capacitances between the bit lines or various kinds of factors associated with the bit lines are remarkably reduced as compared with that generated in the memory of the open bit line structure. Further, a pitch corresponding to two memory cells can be ordinarily set as the pitch of sense amplifiers in the direction substantially perpendicular to the bit line, so that a pattern can be easily designed. Therefore, it is demanded to arrange the folded capacitor cell, vertical capacitor cell, and corrugated capacitor cell to have the folded bit line structure. However, actually, there are various kinds of problems as described above in the case of arranging these kinds of memory cells in the folded bit line structure.